\section{Control state machine}

As was mentioned earlier, the control system is based around a finite 
state machine with 32 states. Therefore the state can be represented as a 
5 bit number which is stored in the 5 D-type flip-flops U2a, U6b, U6a, 
U18b and U2b on the {\bf Control} PCB. The outputs of these flip-flops 
form the address for the 32 byte ROM U12 which contains the state table.

A  description of this state table, which could be considered to be the 
control firmware of the printer, will be given later, but at present only 
the hardware will be described.

The next state is of course determined by the logic levels on the D 
inputs of the flip-flops. The highest 2 state bits are simply determined 
by 2 of the ROM outputs, while the {\bf CC} (Condition Code) signal 
selects one of 2 ROM outputs for each of the lower 3 state bits. For 
example, consider the input to U2a, which holds the lowest state bit. 

If {\bf CC} sis low, then U1d sets {\bf CC/} high. Therefore U1c is 
inhibited and its output is forced high. U1a inverts {\bf SMD(2)} and 
passes it to U1b, which inverts it again., So in this case, the input to 
U2a is {\bf SMD(2)}. If {\bf CC} is high, then U1a is inhibited, while 
U1c inverts and passes on {\bf SMD(7)}, which is then re-inverted by U1b. 
So in this case the input to U2a is {\bf SMD(7)}.

So, depending on the state of {\bf CC}, the new state is given by the SMD 
bits as follows ;
\begin{description}
\item[CC=0]: 6,4,0,1,2
\item[CC=1]: 6,4,3,5,7
\end{description}
There is, of course, no reason why the ROM can't be programmed so the 2 
possible next states have the same value, meaning that the state of the 
{\bf CC} signal is  irrelevant. Needless to say, such unconditional 
transitions are quite common in the state machine. 

The {\bf CC} signal is thus the control input to the state machine. It 
comes from the 16 input multiplexer U14, which selects the various 
signals that need to be tested. The first 8 inputs of this multiplexer 
as used in print mode, the last 8 in input mode, since the D select input 
is driven by {\bf RotEn/}. The other 3 select inputs are driven by 3 of 
the ROM outputs -- thus the next state is partially determined by the 
signal to be tested.

The 16 output decoder U13 is driven by the lower 4 state flip-flops. It 
provided the output signals from the state machine to the rest of the 
logic. Thus each output signal is produced in different stares (since the 
highest state flip-flop is not used by this decoder). However, since 
{\bf SCLk}, the clock signal to the buffer shift register, is required 
in 4 states, 2 of the outputs of the decoder are logically ORed by U20d.

\section{Master Clock and Reset}

The clock for the control state machine comes initially from the RC 
oscillator formed from U8a, U8b and U8c on the {\bf Control} PCB. This 
provides a clock signal of approximately 3.5MHz which clocks the 2 
cross-coupled JK flip-flops U7a and U7b. These cycle through the stares 
00, 10, 11, 01, 00\ldots and thus produce a pair of signals of a quarter 
the frequency of {\bf MCLk} in phase quadrature. The output of U7b is 
used to clock the state machine, that of U7a enables the decoder U13 
when it is low. This has 2 consequences. The first is that the outputs of 
U13 pulse every cycle of the clock divider even if the state machine 
remains in the same state. The second is that the outputs of U13 re 
disabled when the state machine is changing state, thus presenting 
glitches on these outputs.

If the {\bf Wait/} pin on the test connector is pulled low, U20c will 
cause the clock divider to halt in  state with {OutEn/} low, that is with 
U13 enabled. This facility does not seem to be particularly useful.

In order to start the system off in a known state, the {\bf Init/} signal 
is pulsed low by the {\bf Logic PSU} at power-on. This is buffered by 
U27c and U27f on the {\bf Control} PCB and clears all the state 
flip-flops, and other parts of the logic. This also asserts the {\bf Rst} 
signal via U16c, which clears the interface logic. This logic can also be 
cleared by {\bf IFInit}, provided the printer is in input mode -- the 
inverted form of {\bf IFInit} is ANDed with {\bf RotEn/} by U16a.

\section{Interface Handshake}

In order to describe the interface handshake, the particular example of an 
H(830 host will be used. 

The trailing edge of the {\bf LatchEn} signal on the HP9830 {\bf I/O 
Backplane} sets the flip-flop U3a. The Q/ output of this flip-flop goes 
low, causing the printer to appear busy via U1b. The Q output asserts 
{\bf PrtStb/} via U2c.

This strobe signal is fed to the {\bf Control} PCB in the HP9866 where is 
it called {\bf IFStb/}. It is received by U23c, and provided the printer 
has paper and that the manual feed button is not pressed (that is, {\bf 
PaperOut/} and {\bf Feed/} are both high), the output of U22b goes low. 
This is an input to the state machine input multiplexer, U14.

The state machine now begins the character read sequence. When it asserts 
{\bf InCLk/}, the data is latched into the input register. The trailing 
edge of this signal sets U22a on the {\bf Data Path} PCB, which asserts 
{\bf IFFLg/} via U20c. 

Back  on the HP9830 {\bf I/O Backplane}, this flag signal, now  called 
{\bf PFLg/} clears U3a and thus removes the strobe. It also causes the 
busy signal to be maintained via U1b.

When the HP9866 has processed the incoming character, the state machine 
asserts the {\bf CLrFLg} signal. This resets U22a on the {\bf Data Path} 
PCB and de-asserts {\bf IFFLg/}. The printer is now ready for another 
character.

\section{Control Counters}

It is necessary for the control system to keep a count of the number of 
characters stored or printed and the current dot line. In order to simply 
the control system, this information is not stored in the state machine, 
instead separate counters are used. There are 3 such counters,  one 
counts the characters transfered to or from the buffer shift register; 
the second counts the rows of dots being printed and the last is a simple 
4 state counter used to count the shifts when the shift register is moved 
on by 4 characters during each section of the print cycle. These counters 
will be described individually.

\subsection{Character Counter}

the character counter is an 80-state counter consisting of the 
divide-by-10 counter U4 and the divide-by-8 counter U10 on the {\bf 
Control} PCB., It therefore counts from 0 to 79 in BCD.

Two signals increment this counter -- they are logically ORed by U16b. 
During the character input operation, the {\bf PHOut/} signal (which does 
not enable the printhead elements in this mode) is gated via U15d to 
produce {\bf IncCC}. During the print cycle, the {\bf PHClk} signal from 
the state machine, which loads the bit pattern into the printhead shift 
registers increments this counter. It is important to realise here that 
the count is not an `index' of the characters in the data shift register. 
During the print cycle, the bit pattern of every fourth character is 
transfered to the printhead shift register, but the counter is only 
increments once for each character transfered. 

The outputs of this counter are decoded by NAND gates to produce condition
inputs for the control state machine. The output of U16d, {\bf Newbank/} is
asserted when the character count is divisible by 20, that is, when a
quarter of the characters have been transferred to the printhead shift
register, and thus this section of the dot line should be printed. The {\bf 
Char0/} signal is asserted by U9a when the count is zero, that is, when 
the count has wrapped around and all characters have been processed. 
Finally, U15c produces {\bf Fristback/} when the first quarter of the dot 
line is being printed.

Two other circuits are associated with this counter. The SR flip-flop 
produced by cross-coupling U15b and U22c is cleared when a  dot line is 
printed  and set when the character counter is incremented. It thus 
indicates whether any characters have been loaded into the buffer shift 
register. The output of this flip-flop, {\bf Empty/}, is combined with 
{\bf Char0} by U11b.  Its output, {\bf Start/} therefore indicates 
whether the fact that the character counter is 0 indicates. that the 
buffer is full or not 

The other related circuit is located on the {\bf Printhead Driver} PCB. 
Here, the NOR gates in U1 and U2 decode the top 2 bits of the character 
counter, and when {\bf PHEn/} is asserted (the source of this signal will 
be described later), the appropriate bank signal is turned on, energising 
the printhead elements. Since all 4  of these circuits operate in a 
similar manner, only one will be described.

For example, for the second quarter of the line, {\bf PHSelA/} is 1 and 
{\bf PHSelB} is 0. Therefore, when {\bf PhEN/} goes low, the output of 
U1b goes high, the outputs of U2a, U1a and U2b all remain low. The output 
of U1b going high turns on the PNP transistor U8d via U3a and thus 
applies the printhead power supply voltage to the Bank2 signal. 

\subsection{Row Counter}

This is a 10 state counter consisting of U12 on the {\bf Data path PCB}. It 
is incremented by the {\bf RowClk} output from the control state machine 
and keeps a count of the number of dot rows printed. When this counter 
is in state 0, {\bf RotEn} is set low by U19a, selecting the character 
input mode. At the start of the print cycle, this counter is incremented, 
asserting {\bf RotEn} and selecting the print cycle mode. The output of 
U19b goes low during the 7th row of dots; this is the last row and thus 
the state machine tests this at the end of each printed row to check if 
the complete character line has been printed.

\subsection{Shift Counter}

In  order to count the shifts when moving on 4 characters during the print 
cycle, a simple 4 state counter on the {\bf Control} PCB is used. It 
consists of the interconnected D-type flip-flops U17a and U17b. During 
the print cycle, the {\bf ForceSpace/} signal (which has no other use in 
this cycle) increments this counter via U20a. It  counts in the sequence 
00, 01, 11, 10, 00\ldots but the exact sequence is not important for the 
operation of the printer. What is important is that the output of U11a, 
{\bf LnFlg/} is asserted every 4 cycles. This signal is a condition input 
to the state machine.

\section{Timing Monostables}

The  printhead takes a significant time to change the state of the 
thermal paper, similarly the stepper motor takes a significant time to 
move the paper up by one dot row. Three monostable multivibrators are used 
to determine these times.

In order to print the current dot pattern (already loaded into the shift 
registers on the {\bf Printhead Driver} PCB, the state machine asserts 
{\bf PHOut/}. Since {\bf RotEn} is high, the monostable U24 is triggers via 
U20b, thus asserting {\bf PhEN/} for about 6ms. This signal energises the 
printhead elements via the decode circuit on the {\bf Printhead Driver} 
PCB. Monostable U26a is also triggered, it has a time of around 7.16ms. 
This output of this monostable is gated via U25 and synchronised by U18a 
to provide a condition input to the state machine which then waits until 
the printhead has 'burned' the pattern onto the paper before continuing.

Similarly, to move the paper up one dot row, the sate machine produces 
the {\bf AutoFeed/} signal. This triggers the monostable U26b, with a 
period of 8.2ms. This is similarly fed via U25 to the state machine input 
to cause the state machine to wait for the motor to finish advancing the 
paper before attempting to print another row of dots. 

\section{Paper Sensor}

The presence of paper in the printer is detected by a changeover 
microswitch under the chassis. This microswitch is debounced by the SR 
flip-flop U28a and U28b  on the {\bf Control} PCB to produce the {\bf 
PaperOut} signal and its inverse. This signal has 3 effects : It inhibits 
the input strobe signal via NAND gate U22b, thus preventing the printer 
form accepting characters from the host;  It turns on transistor Q1 and 
thus causes the `Load' indicator on the front  of the instrument to 
illuminate; and finally it assets the {\bf IFPout} signal via U20b on 
the {\bf Data Path} PCB to indicate to the host that the paper has run 
out, however this signal is not used by the HP9830. 


