As mentioned earlier, the control system has 2 modes of operation. In the 
first, characters are loaded into the buffer store from the host. In the 
second, the contents of the buffer are printed. The {\bf RotEn} signal 
determines the current mode. This signal is produced by the dot line 
counter. When it is low, the printer is in input mode, and when it is 
high the buffer shift register rotates (hence the name of the signal -- 
ROTate ENable) and the buffer is read out so the contents can be printed. 
A clear understanding of this signal will make understanding the rest of 
the printer much easier.

The 2 operating modes of the data path circuitry will be described 
separately. 

\section{Input Mode}

The input register consists of 7 D-type flip-flops U226, U17, U11 and U6 
on the {\bf Data Path} PCB. Characters are loaded into this register from 
the host by the  {\bf InClk} signal which is derived from an output of 
the control state machine by U21c. Note that the data lines from the host 
({\bf IFD(n)}) are active-low signals, so that the Q outputs of this 
register are also active low, while the Q/ outputs are active-high.

The outputs of 6 of the flip-flops are gated into 6 80-bit shift 
registers, since this printer only handles upper-case characters, 6 bits 
are sufficient. The least significant bit ({\bf InData(0)}) will be 
described, all others are similar. The output of bit 0 of the input 
register, U22b, is fed to the AND-OR-Invert gate U15b. Since {\bf RotEn} 
is low, U20f sets {\bf InEn} high and the data is passed to the input of 
U14b, which is an 80 bit MOS shift register. The clock for this register 
is produced by buffering the {\bf SClk} signal from the control state 
machine with U20a and the transistor Q1. 

At the end of the input line, the remainder of the shift register must be 
filled with space characters. The {\bf ForceSpace/} signal from the state 
machine goes low, and since {\bf InEn} is high, {\bf Space/} is driven 
low by U16a. This logically sets bit 5 of the input register and 
logically clears the remaining bits, thus forcing the register to contain 
the ASCII code for space. The state machine then produces the 
appropriate number of {\bf SClk} pulses to fill the remainder of the 
shift register with space characters

There are 2 circuits that decode the input character and provide inputs 
to the state machine. When a linefeed character is received, the output 
of U5 ({\bf LF}) is asserted (low). This indicates the end of the input 
line and causes the state machine to start the print cycle. 

The other circuit asserts the {\bf PrtChar} (printable character) signal. 
If the character is not a control code (that is, at least one of bits 5 and
6 is asserted, detected by U16d), and it's not DEL (detected by U10) or if
it's a linefeed, the output of U16b goes high, indicating that the
character is to be processed by the printer, this is fed to an input of
the control state machine. 

\section{Print Mode}

In this mode, {\bf RotEn} is high, so {\bf InEn} is set low by U20f. 
Again considering bit 0 of the data shift register, the output of the
shift register U14b is inverted by U7b and fed back to the AND-OR-Invert
gate U15b. This gates this signal back to the input of the shift 
register. Thus the shift register recirculates (rotates) and the data can 
be repeatedly red out. The output of U7b is further inverted by U7a, 
providing an active-high character code bit. The 6 character code bits 
are fed to the low 6 address inputs of the character generator ROM to 
select the appropriate character pattern, the high 3 address lines select 
one row of that pattern and come from the row counter, which will be 
described as part of the control section.

The character generator is U1, and is a 512*8 ROM of the same type as are 
used for the HP9800 firmware. It is permanently enabled ({\bf CE} and 
{\bf CS} are both connected to +12V). 5 outputs of this ROM, containing 
the bit pattern for the current row of the current character are 
inverted, e.g. by U13c, and fed via the backplane to the {\bf Printhead 
Driver} PCB. There are 5 identical circuits on this board, corresponding 
to the 5 dot columns of each character, again only one -- column 0 -- 
will be described.

The {\bf PHData(0)} signal coming into the {\bf Printhead Driver} PCB is
inverted by U4a and fed to the 20 bit shift register consisting of U9 and
U6. The character rows are shifted into this register by the {\bf PHCLk}
signal from the control state machine, inverted by U4b. This shift
register provides 20 of the printhead data signals, those for the first
dot column in each character, {\bf Drv(0), Drv(5)\ldots Drv(95)}. The 5
registers thus provide all100 signals needed to control the selected
section of the printhead. These signals are wired to the connectors for
the 4 printheads. 

Each printhead takes in 25 of the signals and contains circuitry to 
energise the appropriate elements selected by the {\bf Bank0}\ldots{\bf 
Bank 3} signals. Again, the operation of these signals will be described 
with the control logic.



