\section{Introduction}
All the HP9800 machines use the same CPU. It is a 16 bit bit-serial
machine with 2 16-bit accumulators (A and B), a 16 bit program counter
(P), and a 4 bit extension register (E). A 16 bit Q (Qualifier) registers
is used to hold the current machine instruction and for some other
internal purposes. The processor communicates with the machine's memory
via the 16 bit memory address (M) and memory data (T) registers, which are
considered to be part of the memory system and will not be described in
this section. Although it is a bit-serial machine for binary operations,
4 bit BCD operations are possible between the T register and the A
accumulator. 

The processor is controlled by a 256 word microprogram stored in PROMs on 
the CPU control PCB. All HP9800 machines have the same microcode, and 
thus the same machine code instruction set.

\section{Clock generator}
In a bit serial machine, it is frequently the case that the same 
operation has to be performed several times on successive bits of the 
machine word. For example, to increment the value stored in a register, 1 
is added to the LSB and then 0 is added to each of the remaining bits (Of 
course a carry bit is maintained between these bit additions).

(Those who already have some understanding of the machine may look at the
microcode instructions at locations 0202 and 1603 where exactly this
sequence is used to increment the program counter before fetching the next
machine instruction)

There are thus 2 main clock signals in the HP9800. The {\bf Bitclk} 
signal drives the data shift registers and thus causes the current 
operation to be performed on the next bit of the work. The {\bf $\mu$clk} 
signal drives the microcode program counter, causing the next microcode 
instruction to executed. The main purpose of the clock generator circuit 
is to produce {\em m} {\bf Bitclk} pulses followed by a {\bf 
$\mu$clk} pulse. then {\em n} {\bf Bitclk} pulses, and so on, where the 
values of {\em m} and {\em n} are given by the current microinstructions. 
The {\bf LdClk} signal which appears on some of the other PCBs is the 
same as {\bf $\mu$clk}, the signals are linked together on the {\bf CPU 
Clock PCB}.

\subsection{<Master Clock}
We begin on the {\bf CPU Clock PCB}. The master clock is built round U5, 
and provides an 8MHz signal, {\bf MClk}. There is an external clock input 
connector on the top edge of the PCB. Shorting together the 2 
triangular pads on the solder side inhibits U5a and U5b, stopping the 
master clock, while an external clock signal (at TTL levels) can be fed 
in on the pad on the component side to allow the CPU to be run at other 
speeds, or single-stepped, for testing.

\subsection{System Clock Generator}
The central component in the system clock generator is a 4 bit counter,
U5. This is loaded with the number of {\bf Bitclk} pulses needed for the
current microinstruction. Normally the `Br' (Borrow) output is high, so
U7a and U7b are both set, U12a and U13a pass master clock pulses through
to {\bf Bitclk} while U12b and U13b cause {\bf $\mu$Clk} to remain high. 
The counter is decremented on each rising edge of {\bf MClk/}\footnote{A
`/' on the end of a signal name will be used to indicate an active-low or 
inverted signal.}. When the counter underflows, the Br output goes low 
during the low time of the clock input. Thus, on the next rising edge of 
{\bf MClk/}, U7a is cleared, inhibiting the {\bf Bitclk} signal and 
causing {\bf $\mu$Clk} to go low which changes the microcode program 
counter to point to the next microinstruction. Half an {\bf MClk} cycle 
later, U7b is also cleared, loading the new bit count value into U14. 
After another half-cycle, U7a is set, re-enabling U12a (and thus {\bf 
Bitclk}). Finally, after another half cycle, U7b is cleared, the system 
returns to the initial state with the new bit count value in 
U14.

Thus the total number of {\bf Bitclk} pulses between {\bf $\mu$Clk} 
falling edges is one more than the value loaded into U14.

The {\bf Bitclk} signal can be disabled by the IQN signal from the {\bf 
CPU Control} PCB, thus allowing condition control of ALU operations.

\section{CPU control and Microcode}
\subsection{Microcode Word}
The CPU microcode consists of 256 28-bit words stored in 7 PROM chips on 
the {\bf CPU Control} PCB. The microinstruction bits have the following 
meaning : 
\begin{description}
\item[0\ldots 7] : Specify the next microinstruction address. Bits 
0\ldots~3 also specify the condition 
\item[8\ldots 11] : The value loaded into the clock divider 
counter and thus the number of {\bf Bitclk} pulses to be generated in 
this microinstruction, minus 1. 
\item[12] : Read the currently-selected accumulator. If it is 0 and R=0, 
then do a Q$\mu$jmp (this will be explained later). If it is 0 and R=1 then 
begin an input/output operation
\item[20, 13, 14] : Specify the operation to be performed by the ALU
\item[15] : Apply the selected condition to the {\bf Bitclk} signal, known 
as {\bf IQN} in some HP manuals
\item[16\ldots 18] : R field. This is mainly used to select one of the 
ALU inputs, but other functions are controlled here too. It will be 
described further below. Note that bit 16 is the MSB (and bit 18 the LSB) 
of this field.
\item[19] : Use the currently-selected condition to control the next 
microcode address
\item[21\ldots 23] : X field. This is used to specify the destination of 
the ALU output and various other operations. It will be described below. 
In this field, the bits should be taken in the order 22, 21, 23
\item[24, 25] Specify the source for the second ALU input. This will be 
described as part of the memory circuitry
\item[26] : Load the T register (Memory data) from the ALU output
\item[27] : Load the M register (Memory address) from the ALU output
\end{description}

As an aside, the microcode PROM enable signal ({\bf ROME/} is asserted by
a 33$\Omega$ resistor on the {\bf Data Path} PCB. The PROMs are normally
always enabled, but could be disabled for factory testing. 

\subsection{Microcode Sequencer}
The microcode address is provided by the 8 JK flip-flops in U8, U9, U16 
and U17. The J and K inputs of each flip-flop are connected together, 
thus turning them into toggle flip-flops. If this combined input is low, 
then that flip-flop does nothing when clocked by the falling edge of 
$\mu$clk, whereas if it's high, the flip-flop will change state.

All these flip-flops are cleared (and thus all the microcode address bits 
set to `1') by the {\bf Init} signal from the power supply. This starts 
the microcode at the correct address when the machine is turned on.

For the moment, ignore U15, and assume that it simply passes the signals 
on its `1' inputs through to its outputs. Thus the top 7 bits of the 
microcode address are directly controlled by the current microcode word 
address field. If a bit in this field is a `1', then the appropriate bit 
of the address is changed for the next microinstruction.

The lowest microcode address bit can be modified by a condition code (the
{\bf CC/} signal). If microcode bit 19 ({\bf $\mu$(19)}) is `0', then U11a
is inhibited, so the output of U1d is forced high. In this case, the
condition is not used, the change to address bit 0 is specified by {\bf 
$\mu$(7)} only. But if {\bf $\mu$(19)} is `1', U11a is enabled, so the 
{\bf CC/} signal is passed on to U11b. Thus whether or not the lowest 
microcode address bit is changed depends on the state of the {\bf CC/} 
signal.

Multiplexer U3 is the source of the {\bf CC/} signal. It selects one of 16 
conditions controlled by the value of the lowest 4bits of the current 
microinstruction. Ten of these conditions are bits in the Q register, The 
remaining 6 are the low bit of the program counter (8); the output of U4b 
(which indicates when the current machine instruction in the Q register is 
a memory reference instruction) (10); the binary (7) and decimal (14) carry 
flags; that an I/O operation is in progress (15); and finally that an 
interrupt has been received (12). (Numbers in parentheses indicate the 
input of U3). 

Now consider U15, which is a 2-input multiplexer. Normally, as I 
suggested earlier, it causes the microcode address to be updated by the 
appropriate bits of the current microinstruction. But if the {\bf 
Q$\mu$Jmp/} signal is asserted (low), then the top 4 bits of the microcode 
address are changed based on the value in the Q register. This is used 
as a multi-way microcode branch for decoding the current machine code 
instruction. The {\bf Q$\mu$Jmp/} signal comes from U15b on the {\bf Data 
Path} PCB and is asserted if microcode bit 12 is 0 and the R field 
contains 1 (as noted above).

Another simple microcode function uses U4a. This NAND gate makes the {\bf
IQN} signal low, inhibiting the {\bf Bitclk} signal if the
microinstruction bit 15 is high and the {\bf CC/} signal is not asserted
(that is, CC/ is high). 

There is a very useful test connector on the top of the {\bf CPU Control}
PCB. It carries the microcode address bus, and many of the signals used to
update the microcode address. Connecting a logic analyser to the microcode
address bus will be suggested in a later article as a way of finding out
just what the CPU is doing. 

\subsection{R and X field decoding}
The R field is decoded by the 1-of-8 decoder U18 and the X field is 
likewise decoded by U10. The R field has the following meanings : 
\begin{description}
\item[R=0] : Force `1' into ALU input
\item[R=1] : Read P register (Program counter) into the ALU
\item[R=2] : Shift T into the E register and E into the ALU
\item[R=3] : Memory Write cycle
\item[R=4] : Transfer ALU output to bit 6 of the Q register
\item[R=5] : Read Q register into the ALU
\item[R=6] : Memory Read cycle
\item[R=7] : None of the above, used to force a '0' into the ALU input
\end{description}

\noindent
While the X field has the following meanings : 
\begin{description}
\item[X=0] : Shift ALU output into the Q register
\item[X=1] : Set the accumulator selection flip-flop from bit 11 of the Q 
register and clear the decimal (BCD) carry flag
\item[X=2] : Perform ALU decimal (BCD) operation
\item[X=3] : Shift ALU into the E register and E into the ALU
\item[X=4] : Invert the accumulator selection flip-flop
\item[X=5] : Shift ALU into the P register
\item[X=6] : Shift ALU into the currently-selected accumulator
\item[X=7] : None of the above
\end{description}

This is one odd case. If X=3 and R=2, then the output of the ALU is 
shifted into the selected accumulator rather than E. E is read into ALU 
as expected, but the input to the E register is forced to 0. 

\subsection{Q Register}
It is arguable whether the Q register should be covered here or in the 
date path section. For no better reason that it's located on the {\bf CPU 
Control} PCB, I will describe it here. The Q register is a 16 bit shift 
register made from 4 4-bit devices. The control signals are not simply 
linked together (as would be conventional), so the operation of this 
register requires some explanation. 

There are 3 operations that can be performed with the Q register (other 
than using its parallel outputs, e.g. as inputs to the microcode 
condition multiplexer) : 

The Q register can be loaded from the ALU output. In this case, the X 
field contains 0, so {\bf X(0)} is asserted (low). This enables the clock 
to all sections of the register via U4c and U11c, and all the mode inputs 
are low. Thus the register shifts one bit to towards the bit 0 end on 
each {\bf Bitclk} cycle, and the output of the ALU {\bf ALU(0)} is loaded 
into the most significant end of the register.

The Q register can be read into the ALU. The operation on the Q register 
itself is to rotate it one bit towards the bit 0 end on each {\bf Bitclk} 
pulse. In this case, {\bf R(5)} is asserted (low). The clock is enabled as 
before, but this time the mode input of the most significant device (U3) 
only is high. This causes this device to perform a parallel load 
operation, which owing to the connections to its inputs actually causes 
it to shift one bit towards the least significant end and load bit 0 into 
the most significant location. In other words the Q register rotates as 
required

Bit 6 (only) may be loaded from the ALU output. Now {\bf R(4)} is 
asserted, so the output of U1e is high. The main clock is disabled, but 
U13 gets a load clock from the {\bf LdClk} signal at the end of the 
microinstruction. Thus U13 parallel-loads. Three of its bits are simply 
copied back into itself, but the B input, corresponding to bit 6 of the Q 
register, is driven by the ALU output.

