\section{The HP9810 Memory System}
The memory system of the HP9810 is unconventional in that a 1K*1 bit RAM 
chip appears as a 512*2 bit device. The 16-bit wide system RAM uses only 
8 chips, for example.

\subsection{M register and address decoder}
The M register is a 16 bit shift register formed by cascading U2, U3, U8 
and U1 on the {\bf Memory Address} PCB. To load it from the ALU output, 
microcode bit {\bf $\mu$(27)} is low> This enables U9d, which passes the 
{\bf Bitclk} signal to the shift register. The mode input is low, so the 
register shifts right on each {\bf Bitclk} pulse, and the ALU output is 
shifted into the most significant end. 

To read the register, the S field contains 1. This is decoded by U16c on 
the {\bf Memory Timing} PCB, and the {\bf RotEn} signal is high. Back on 
the {\b Memory Address} PCB, U9c is enabled, and for a simple read, the 
mode input of the shift register is high. The register thus 
parallel-loads on each {\bf Bitclk} pulse, but owing to its connections, 
this results in a rotation to the right.. The LSB of the register is 
transfered to the ALU via the first gate of the AND-OR-Invert gate U17 
on the {\bf Memory Timing} PCB, enabled by the {\bf RotEn} signal.

The 2 operations can occur simultaneously. In this case, the register 
performs a serial load operation, and the LSB is transfered to the ALU 
via the AND-OR-Invert gate.

The parallel outputs of the M register are decoded to provide chip-select 
signals for the ROM and RAM devices. The output of U9a is asserted (high) 
when the high nybble of the address is X000. This enables the decoder U17 
via U11a when the {\bf MemEn} signal is high. This signal, from U11b, is 
asserted if the R field contains 3 or 6, corresponding to memory read or 
write operations. Similarly, U10 is enabled via U9b and U11d when the 
high nybble of the address is X001. These decoders thus divide the lowest 
8K words of the processor address space into sixteen 512-word blocks, 
which is the size of either a pair of ROMs or a set of RAMs. 

The ROM selection outputs from these decoders are converted to 12V levels 
(as required by the ROM chips) using open-collector inverter and 
transistor circuit such as the one built round U15f. When the chip select 
line is not asserted, the input to U15f is high, so the output, and the 
select input to the ROM are low. The transistor is cut off. When the 
input to U15f goes low, its output is pulled high by the 4k7 resistor, 
the transistor is turned on, bringing the ROM select line to +12V, 
enabling that ROM

In a similar way, the RAM selection outputs are converted to 16V levels. 
For example, the {\bf RawRAMCS(0)} signal from the decoder is logically 
ORed with the {\bf Rfsh/} signal by U11c, the output of this gate will be 
high as will the output of U12b if the {\bf RAMStb} signal from the 
memory timing PCB is high. The output of U12b is inverted and converted to 
16V levels by U18e and a complementary pair of emitter-followers.

The {\bf RAMEn} signal, from the NAND gate U4, is asserted if any of the 
RAM areas are selected.

The lower 9 outputs of the M register are used to select a location 
within a memory device. In the case of the ROM, the lowest 8 bits are 
simply buffered, for example by U7c, these NAND gates being enabled by 
the {\bf MemEn} signal, delayed by U5a and an RC timing network. Bit 8 
is used to enable one or other half of the ROM as described in the 
introduction, these 2 signals are produced by U13a and U13b, enabled 
by U14b, which occurs during the later part of a memory cycle ({\bf 
ROMEn/} asserted) which doesn't address a RAM block.

The RAM addressing is slightly more complicated since, being dynamic RAMs, 
a refresh address has to be generated too. The top 5 address lines are 
converted to 16V logic levels by circuits such as the one based round 
U20f and sent to the RAM board (this circuit, of course, operates in the 
same manner as the ROM selection buffers). The low nybble of the M 
register is fed to the {\bf Memory Timing} PCB, where it enters the 
AND-OR-Invert gates U14 and U15. These act as multiplexers, switching the 
RAM address buffer inputs between the output of the M register and the 
output of the refresh address counter, U13. RAM address input 4 ({\bf 
RAMAddr(4)}) is used to select between the 2 half-width locations storing 
a word, and will be described below.

\subsection{T Register}
The `T', or Memory Data, register is located on the {\bf Memory Data} 
PCB, and consists of the four 4-bit registers at locations U1, U6, U11, 
and U14 cascaded in the conventional way. The serial input/output 
facilities of this register are used to communicate with the bit-serial 
processor, the parallel signals are used to communicate with the memory 
device data bus. 

To load the T register from the processor, microcode bit {\bf $\mu$(26)) 
is low. This causes the output of U21a on the {\bf memory Timing} PCB to 
go high, enabling U11c and passing the (\bf Bitclk} signal to the T 
register. The top gate of the AND-OR gate U22 on the {\bf Memory Timing} 
PCB is enabled, so the output of the ALU is gated to {\bf TRegSin} and 
thus loaded into the register.

To read the T register into the processor, the S field contains 2. This 
causes the output of U16d on the {\bf Memory Timing} PCB to go high, 
which enables the T register clock via U21a and U11c as before. Now the 
second gate in U22 is enabled, so the LSB of the T register ({\bf T(0)}) 
is gated back to the serial input, the register rotates. The second gate 
in the {\bf ALUSerIn} data selector, U17, is enabled so the LSB of the T 
register is transfered to the ALU input.

If both operations occur simultaneously, then only the first gate of U22 
is enabled so the T register is loaded from the ALU as before, but the 
second gate of U17 is also enabled, so the LSB of the T register is 
transfered to the ALU input. 

As an aside, the third gate in U17 is used for force a `1' into the ALU 
input when the S field contains 3 and the fourth gate feeds the serial 
output of the I/O register on the {\bf I/O Interface} PCB into the ALU 
when enabled by the I/O control circuitry during input instructions.

The parallel interface between the T register and memory will be described 
below.

\subsection{Memory timing and control}
The memory timing circuit is based around the 4-bit counter U5 on the 
{\bf Memory Timing} PCB. The outputs of this counter are decoded by U10, 
giving the {\bf State(n)} signals. Normally this counter is held reset by 
U4c, since both {\bf State(0)} and the output of U12b are low. A memory 
cycle is stated by the {\bf MemEn} signal going high. This forces to the 
output of U12c high and that of U12b high. The reset input of the counter 
thus goes low, and the counter starts counting, the {\bf State(n)} lines 
going low in sequence. The output of U12b goes low again when the 
memory accessing microinstruction ends after 12 clock cycles, but the 
output of U4c remains low until the {\bf State(0)} signal goes low again. 
The system is now back in the initial state, ready for another memory cycle.

There are 3 types of memory access operation : 

\subsubsection{ROM Read}
In state 4, and all subsequent states, the output of U21d goes high, 
asserting {\bf ROMEn/} via U23c and bringing {\bf ROMCE} from 12V to 0V. 
The ROM address lines are enabled as described above. Since this is a 
read operation, {\bf R(6)} is low, so {\bf TMode} is driven high by U16b, 
setting the T register for parallel loading. The T register is loaded by 
the {\bf TLd} signal, in state 5 (which is essentially a dummy operation) 
and again in state 11, due to U3b, U11d and U11b. Since {\bf R(3)} is 
high. {\bf THold} is forced low by U16a and since U2a is never set, {\bf 
TShift} is also kept low.

On the {\bf Memory Data} PCB, the {\bf RAMEn} signal is low, so the RAM 
Read buffers are disabled. Thus (considering bit 15), the output of U16C 
is high, the ROM data passes through U2b into the T register. In the case 
of bit 14, both U5c and U5d are disabled, their outputs are `1', so U2a 
passes the ROM data into the T register. The other bits follow the same 
pattern.

\subsubsection{RAM Read}
The RAM read cycle has to be considered one state at a time (All ICs are 
on the {\bf Memory Timing} PCB unless otherwise specified) :  
\begin{description}
\item[State 2] : U8a is cleared by U3d, thus asserting {\bf RAMStb} and 
enabling the selected RAM via the gates on the {\bf Memory Address} PCB. 
U8b is directly set, so the {\bf Precharge} input to the RAM goes high.
\item[State 5] : U8a is set, deasserting {\bf RAMStb}. {\bf TLd} is
asserted via U3b U11d and U111b, the RAM data outputs are converted to TTL
levels on the Memory Data PCB (e.g by U18b) and transfered to the
odd-numbered bits of the T register, the {\bf ROMD} lines all being high
since no ROMs are enabled.. 
\item[State 6] : U8b is cleared by U3c, thus the {\bf Precharge} signal 
goes low. U9b is toggled via U23f, thus {\bf RAMAddr(4)} goes high, 
selecting the location containing the other half of the word.
\item[State 8] : U2a is set via U11a, thus asserting {\bf TShift} (which 
remains asserted for the rest of the cycle).
\item[State 9] : U8a is again set, this is a repeat of State 2 to read 
the second half of the word.
\item[State 11] : The {\bf TLd} signal is again asserted by U3b, U11d and 
U11b. The RAM outputs are transfered to the odd-numbered bits of the T 
register as in state 6, but since {\bf TShift} is asserted, the transfer 
gates, for example U5c on the {\bf Memory Data} PCB are enabled and the 
existing contents of the odd bits of the T register are transfered to the 
even bits.
\item[State 12] : U8a is set, disabling the RAM select signal.
\item[Sate 15 and end of cycle] : All flip-flops are returned to their 
initial states, the state counter is halted.
\end{description}

Thus, at the end of the cycle, The 2 register contains the contents of 
the first location read ({\bf RAMAddr(4)}=0) in its even-numbered bits 
and the contents of the second location read ({\bf RAMAddr(4)}=1) in its 
odd-numbered bits.

\subsubsection{RAM Write}
The operation of the {\bf RAMStb} and {\bf Precharge} signals is 
identical to a read cycle. U16a brings {\bf THold} high during states 
0-7, since {\bf R(3)} is low.
\begin{description}
\item[State 2] : RAM selected and Precharge brought high as before
\item[State 4] : Since {\bf THold} is high and {\bf TShift} is low, the 
even-numbered bits of the T register are applied to the RAM data inputs 
via, e.g., U5d and U10d on the {\bf Memory Data} PCB. U9a on the {\bf 
Memory Timing} PCB is cleared for one cycle, pulsing the {\bf R/W/} 
signal low and writing this data into the RAM.
\item[State 5] ; U8a is set, removing the RAM select signal
\item[State 6] : U8b is cleared, removing the {\bf Precharge} signal. U9b 
is set to select the second RAM location to be used (as above)
\item[State 8] : U16a is now disabled, so {\bf THold} goes low. U2a is 
set via U11a, so {\bf TShift} goes high/
\item[State 9] : Start the second RAM cycle, as in State 2
\item[State 11] : Since {\bf TShift} is high and {\bf THold} low, the 
odd-numbered bits of the T register are gated to the RAM inputs (e.g. via 
U5c and U10c on the {\bf Memory Data} PCB). U9a is cleared for one cycle 
(as in State 4) thus writing the odd-numbered data bits to the RAM.
\item[State 12] : Set U8a to disable the RAM select signal as before
\item[State 15 and end of cycle] : All flip-flops are returned to their 
initial conditions ready for another cycle.
\end{description}

Thus, at the end of the cycle, the even numbered bits of the T register 
have been stored in the first RAM location ({\bf RAMAddr(4)}=0) and the 
odd-numbered bits of T in the second RAM location ({\bf RAMAddr(4)}=1), 
as required for them to be correctly read back by a RAM Read cycle.

\subsection{RAM Refreshing}
The dynamic RAM ICs used in the HP9810 need to be refreshed and this is
performed by circuitry on the {\bf Memory Timing} PCB. 

The monostable U1 sets the time between refresh cycles. When it times 
out, it causes U6a to be set, thus removing the rest signal from U6b. At 
the end of the next microinstruction, the {\bf RfshSt} signal is asserted 
via U12d and U4d, so U6b is set. Thus the output of U18a goes high, 
asserting the {\bf Rfsh} signal and inhibiting the microcode clock via U20d.

When {\bf Rfsh/} is low, the reset input of the state counter is also low,
thus this counter free-runs. The memory timing circuitry performs dummy
RAM ready cycles. U9a is held set, so the {\bf R/W/} input to the RAM can
never go low and writing is thus impossible. U16b is inhibited, so no data
is transfered to the T register. RAM address bit {\bf RAMAddr(4)} is 
provided by U9b as usual. 

The AND-OR-Invert gates U14  ad U15 switch the low 4 RAM address lines 
from the outputs of the M register to the outputs of the 4-bit counter 
U13. This is incremented at the end of every complete refresh memory cycle 
by U12a. When all 32 addresses have been accessed, as required by the 
RAM's specifications. (a total of 16 cycles), {\bf RfshCy} goes low. This 
triggers U1, deasserting the {\bf Rfsh} signal. The machine then
continues running until U1 times out again and the RAM is refreshed once 
more.

\subsection{Memory PCBs}
The ROM and RAM PCBs, along with the plug-in ROM modules simply contain 
the appropriate memory devices and little more needs to be said about 
them. One minor curiosity is that the user program in the HP9810 is 
stored as a sequence of 6-bit keycodes, and thus the program storage RAM 
is logically 6 bits wide. Due to the fact that the physical RAM width is 
half the logical RAM width, the program RAM is expanded in multiples of 3 
chips. I suspect this is the only machine where this is the case.

\subsection{Memory system test connector}
There is a test connector on the top edge of the memory box backplane in 
both the HP9810 and HP9820 machines. It carries the parallel outputs from 
the M and T registers and can be used to check the proper functioning of 
these registers or to trace machine code programs. The pinout of this 
connector is the same in the 2 machines.
