\section{The HP9820 Memory System}
The HP9820 uses 16-bit wide memory throughout, both ROM and RAM. This 
simplifies the design of the T register and memory timing circuits, but 
causes additional complexity in the address decoder. 

\subsection{M register and address decoder}
The M register itself is located on the {\bf Memory Address} PCB, and is 
very similar to that in the HP9810. It is a 16 bit shift register formed 
by cascading U4, U3, U9 and U2. It is serially loaded from the ALU output 
when the microcode bit {\bf $\mu$(27)} is low, This enables the {\bf 
SRClk} signal via U10a and U122. The mode inputs of the shift registers 
are low, so the register shift right and the output of the ALU is loaded 
into the MSB.

When the S field contains 1, the output of U6b on the {\bf Memory Timing} 
PCB goes high. This enables U12a on the {\bf Memory Address} PCB. The M 
register rotates as described in the case of the HP9810. The LSB of the M 
register is transfered to the ALU via the second gate of the 
AND-OR-invert gate data selector U25 on the {\bf Memory Timing} PCB, 
enabled by U6b. As in the HP9810, simultaneous reading and writing are 
possible, and operate in the same way as in that machine.

The parallel outputs of the M register are decoded and used to enable the 
various memory devices. The output of U5c on the {\bf Memory Address} PCB 
goes high when the address is in the first 4K of the address space, and 
thus decoder U14, enabled by U23d, decodes this part of the space into 
512-word blocks. Of course {\bf Memcycle}. the output of U23d is high for 
a memory cycle when the R field contains either 3 or 6. The output of U5a 
is high for addresses of the form $00xxxxxxxxxxxxx_2$ or 
$0x000xxxxxxxxxx_2$. Since in this part of the address decoder, the 
output of U5a is ANDed with {\bf M(12)} by U12, the second group of 
addresses is masked out here, and the decoder U15 decodes the second 4K 
part of the address space.

\subsubsection{ROM addressing}
There are 14 ROM blocks in the HP9820 (8 for the system ROMs and 2 in 
each of the 3 plug-in modules). Thirteen of these blocks are selected by 
outputs of these decoders, which are buffered to the required 12V levels 
by inverter and transistor circuits, such as that built round U19b on the 
{\bf Memory Address} PCB. The operation of this circuit has been 
described as part of the HP9810 memory system.

ROM 1 is the exception to this. It appears in the first half of blocks 1 
and 14. When either block is selected, the output of U16d goes high. If 
{\bf M(8)} is also low (signifying the first half of a 512-word block), 
the output of U10f will also be high. This enables ROM 1 via U1d and U19e.

The lowest address lines are passed through e.g. U1b (enabled whenever a 
memory cycle is occurring) and fed to the ROM devices. Address line 8 is a 
little more complicated. Normally, {\bf RawCS(14)} is high, thus the 
output of U16 is the same as {\bf M(8)}. This is used by U13a and U13b to 
enable the appropriate half of the ROM when {\bf ROMHAddrEn} is high. 
This comes from U17b, and occurs during a memory cycle which does not 
access RAM (and therefore accesses ROM). When {\bf RawCS(14)} is low -- 
when the second half of ROM 1 is accessed, then ROM address input 8 is 
forced high by U16a, thus selecting the second half of ROM 1 (of course, 
during accesses to the first half of block 1, {\bf M(8)} is low anyway, 
thus selecting the first half of ROM 1 here).

The output of U17d ({\bf StatEN}) goes high when the last word of the ROM 
in block 1 is read. This word is modified if an extension RAM PCB is 
fitted to the machine by logic on the {\bf Memory Data} PCB.

\subsubsection{RAM addressing}
The standard 1K words of RAM appears in the second half of block 1, the 
second half of block 2 and all of block 15. The output of U16d is high 
whenever blocks 1 or 14 are accessed, and thus the output of U18c is high 
whenever the second half of either of these blocks is accessed. The output 
of U17a is clearly high when block 15 is accessed. These are logically 
ORed by U17c, the output of which goes low to enable the standard RAM. 

The expansion RAM (also 1K words in size) is enabled for addresses of the 
form $01000xxxxxxxxxx_2$ by U12b and U23c. When either RAM area is 
accessed, the output of U16c goes high, enabling the RAM output buffers 
on the {\bf Memory Data} PCB and disabling ROM access via U17b.

The outputs of the RAM decoders are logically ORed with the {\bf Rfsh} 
signal (so that all RAM is enabled on a refresh cycle) by U11c and U11d, 
and then ANDed with the memory timing signal {\bf RAMCSEn} by U18d and 
U18a. They are then converted to 16V levels and fed to the RAM chips.

The address lines to the RAM chips Fit into 3 groups. {\bf M(0)}\ldots{\bf 
M(4)} are fed to AND-OR-Invert gates on the {\bf Memory Timing} PCB (e.g 
U22a) which elect between the M register outputs and the refresh address 
counter. The outputs of those are buffered to 16V levels (e.g. by U17a) 
and fed to the RAMs, as described in the HP9810 memory system.

{\bf M(5)}\ldots{\bf M(7)} are simply converted to 16V levels on the {\bf 
Memory Address} PCB (e.g.by the circuit around U21e) and fed to the RAMs.

The highest 2 RAM address line circuitry is also on the {\bf Memory 
Address} PCB but is made more complicated by the fact that the standard 
RAM is split between 3 blocks. When block 1 is accessed, U16b and U11b 
are inhibited, so the outputs of both are high. When the second half of 
block 14 is accessed, the output of U16b goes low, that of U11b is high 
(by virtue of the fact that {\bf M(9)} is low in block 14). And throughout 
block 15, the output of U16b is the inverse of {\bf M(8)} while U11b's 
output goes low (since {\bf M(9)} is high as is {\bf RawCS(1)}). Thus a 
different 256 words of RAM are accessed in each case. When the expansion 
RAM is accessed, the outputs of U16b and U11b are simply the inverses of 
{\bf M(8)} and {\bf M(9)}. 

\subsection{T Register}
The T register is a 16 bit shift register comprising U2, U5, U3 and U4 on 
the {\bf Memory Data} PCB. As in all HP9800 machines, it communicates 
serially with the processor while the parallel inputs and outputs are 
used for the parallel memory data bus.

To load the T register from the processor, {\bf $\mu$(26)} is low, This
enables the {\bf Bitclk} signal to the R register via U7c, U11b and U13a
on the {\bf Memory Timing} PCB. The ALU output is passed to the MSB of the
T register via the third gate in the AND-OR data selector U18 on the {\bf
Memory Timing} PCB, so data is transfered from the ALU to the T register. 

To read the T register into the ALU, the S field contains 2. This causes 
the output of U9d on the {\bf Memory Timing} PCB to go high, enabling the 
T register clock as before. The second gate in U18 is enabled, so the T 
register recirculates (the LSB output is fed back to the serial input). 
The fourth gate in the ALU data selector U25 is enabled so the serial 
output of the T register is read into the ALU.

If both operations are requested at the same time, the T register is read 
into the ALU as normal, but the third (not the second) gate of U18 is 
enabled, so the T register is loaded from the ALU output.

The remaining gates in U18 allow the T register to be loaded from an 
external DAM device (fourth gate) or to recirculate when being read by a 
DMA device (first gate). Little more will be said about DMA devices here, 
since I have never seen one and thus have no precise details on how they 
operate.

There are 2 remaining gates in U25. The first gate is used to force a `1' 
into the ALU when the S field contains 3. The third gate transfers the 
I/O register contents to the ALU under the command of the input/output 
system. These operate identically to their counterparts in the HP9810.

The parallel outputs of the T register are converted to the RAM's 16V
levels, e.g. by the circuit containing U8c, and fed to the data inputs of
the RAMs. 

The data outputs from the RAMs are converted to TTL levels by the 
comparator circuits such as U14a, which are enabled when the RAM is 
accessed. The outputs are then inverted and logically ORed with the ROM 
data outputs, for example by U16, and fed into the parallel inputs of the 
T register. Since ROM and RAM are never both enabled at the same time, 
this simply passes the data from an enabled memory device, unchanged, to 
the T register.

There is one exception to this. {\bf TIn(10)} will be forced high by U10
when the last word of the ROM in block 1 is read (that is, when {\bf
StatEn} is asserted) and if an expansion RAM board is fitted (when U11a's
output is high since its input is connected to ground by track on this
extension RAM board). Thus the machine can tell if the board is present.

The timing of the parallel load will be described in the next section.

\subsection{Memory timing and control}
The memory timing circuit is again based around a 4 bit counter, U1 on the 
{\bf Memory Timing} PCB, the outputs of which are decoded by U5. Normally 
the counter is held reset by U6a, but when a memory cycle occurs, the 
output of U7d goes high, releasing the reset condition. The counter thus 
counts until {\bf State(0)} goes low at the end of the cycle. The {\bf 
ROMEn/} signal is asserted by U11d and U21f when the state counter gets to 
state 4, and remains asserted for the rest of the cycle.

There is essentially only one type of memory cycle in the HP9820, which 
occurs as follows : 
\begin{description}
\item[State 1] : U16b is set, removing the reset signal from U15a and 
allowing the {\bf Precharge} signal to be asserted later.
\item[State 2] : Start of the dummy RAM cycle, used only during refresh. 
U15b is cleared, asserting {\bf RAMCSEn}, setting U15a via U9b and thus 
asserting {\bf Precharge} to the RAM
\item[State 5] : Set U15b, deasserting {\bf RAMCSEn} and removing the set 
signal from U15a. End of the first RAM cycle.
\item[State 6] : Clear U15a, deasserting {\bf Precharge}. Toggle U4a. This
is a remnant of the half-width RAM addressing of the HP9810, and is used 
here only to supply a bit of the refresh address and thus refresh two RAM 
locations in a single refresh cycle. 
\item[State 9] : Clear U15b, starting the second RAM cycle as in state 2. 
\item[State 11] : On  RAM write cycle, U16a is toggled low for 1 clock 
cycle (the output of U22a is high), so {\bf RAMWr/} is asserted, writing 
the data to RAM. For read cycles, {\bf TMode} is high (since U12d's 
output is high), and thus {\bf TLd} pulses high in this state. This 
parallel-loads the T register with the contents of the selected ROM or 
RAM location.
\item[State 12] : End of the second RAM cycle, as state 5. 
\item[State 15 and end of cycle] : All flip-flops are returned to their 
initial states, ready for another cycle, the counter is halted.
\end{description}

Thus at the end of the cycle, the appropriate transfer between the T 
register and memory has occurred.

\subsection{RAM Refresh}
The Dynamic RAM refresh circuit is located on the {\bf Memory Timing} 
PCB. A discrete transistor astable multivibrator releases normally holds 
U4b reset. When a refresh cycle is to occur, this reset is released, and 
at the end of the next microinstruction, U14b is set, asserting the {\bf 
Rfsh} signal and inhibiting the microcode clock via U19c. When {\bf Rfsh} 
is asserted, the reset input of U1 is held low via U7d and U6a, so the 
memory state counter runs. As described above, 2 memory cycles are 
performed for each complete cycle of this counter. {\bf RAMWr} is 
inhibited since U16a is held in the set state and T register loads are 
inhibits via U12d and U8a. Thus no actual data transfers occur in these 
cycles.

The AND-OR-invert data selectors such as U23 switch the low 5 RAM 
address lines from the outputs of the M register to the outputs of the 
refresh address counter on the {\bf Memory Timing} PCB. The LSB of the 
refresh address is provided by U4a, which as described above is toggled 
during the state counter cycle. The remaing 4 bits are provided by a 4 
bit counter, U20, which is incremented at the end of each state counter 
cycle. Thus all 32 refresh addresses are generated in sequence. When all 
locations have been refreshed, U14a is set via U21a, inhibiting U9a, 
deasserting {\bf Rfsh} and enabling the microcode clock/ U14a is cleared 
when U14b is cleared by the multivibrator, ready for another refresh cycle.

\subsection{DMA flip-flop}
Since I do not own a DMA peripheral, I am unable to describe DMA cycles 
in detail. However, since this flip-flop disables the system microcode 
clock, it will be described.

The DMA control flip-flop is U4b on the {\bf Memory Timing} PCB. When a 
memory cycle is not occuring ({\bf Memcycle} is low), it is held reset. 
Therefore, when a memory cycle begins, both inputs of U13c are high and 
thus {\bf Dis$\mu$Clk(2)} goes low, This would inhibit {\bf $\mu$Clk} via 
U12b on the {\bf Clock} PCB.

However, if no DMA operations are occuring, {\bf EMB/} is high. 
Therefore, when U4a is set during the memory cycle, the output of U9c 
goes high amd U4b is set. This re-enables the microcode clock before the 
start of the next microinstrucion, in fact this flip-flop has no real 
effect on the machine. But during DMA operations, will rempain clear, 
preventing further microinstructions from being executed untl the DMA 
operation has completed.

\subsection{Memory PCBs}
As in the HP9810, the HP9820 memory PCBs contain the appropriate memory 
devices only. The standard and expansion RAM PCBs are identical and 
simply contain sixteen 1103 DRAM devices. The 2 ROM PCBs are electrically 
identical both to each other and to the HP9810 ROM PCB. The boards differ, 
of course, in the programming for the ROM devices fitted, and also in the 
part numbers, both for the complete PCB and the ROMs themselves that are 
etched on the board. The optional ROM modules again are electrically 
identical to those in the HP9810, but of course with different ROMs.

\subsection{Memory system test connector}
The test connector on the top edge of the memory box is identical in 
connections and function to that on the HP9810 memory box.
