Since the HP9800 machines use volatile semiconductor RAM, a magnetic 
backing storage system was fitted to all models so that programs and data 
could be saved and reloaded. The HP9810 and HP9820 have a magnetic card 
reader, the HP9830 has a digital cassette tape drive.

\section{HP9810/HP9820 Magnetic card reader}
The magnetic card reader records 3 data tracks and a clock (also known 
as `timing' or `strobe') track in each direction on a magnetic card. The 
system consists of a motorised mechanism to pull the card past the 4-coil 
head and the {\bf Card Reader Interface} PCB which links the mechanism to 
the processor {\bf I/O Interface} PCB. 

\subsection{Card reader mechanism}
The card reader mechanism consists of a 24V DC permanent-magnet motor 
with an integral gearbox, the output shaft of which is coupled to the 
card feed roller via a belt drive. This roller draws the magnetic card 
past a read/write head. Four optical sensors, each consisting of a 
filament lamp and a photodetector located so that the card blocks the 
light beam as it passes detect the leading and trailing edges of the card 
and also the presence or absence of a notch in the leading edge of the 
card, used to write-protect it.

\subsection{Card reader interface}
The {\bf Card Reader Interface} PC is quite simple because most of the 
timing is controlled by the processor firmware..

There are 2 outputs from the {\bf I/O interface PCB} used to select the
card reader. {\bf CROut} is asserted by U19a on this PCB when {\bf
I/OCmd(3)} and {\bf Q(1)} are both high, that is when an `STC' machine is
executed with internal select code 2. {\bf CRSOut} is asserted by U1c
when {\bf Q(1)} and {\bf RdInst} are high. The latter signal is asserted
by U8d on the {\bf Clock} PCB when {\bf Q(9)} is low and {\bf I/OCmd(0)}
is asserted. So {\bf CRSOut} is asserted when an `STF' instruction with
select code 2 is executed. These 2 signals write the low 6 bits of the
processor I/O register into a 6 bit output port built form D-type 
flip-flops on the {\bf Card Reader Interface} PCB. 

Bit 5 of the I/O register is loaded into U5a by {\bf CROut}. The output of
this flip-flop is buffered by a 2-transistor circuit which connects the
positive side of the motor to the +12V supply when the flip-flop is set. 
Since the negative side of the motor is connected to the -12V rail, 24V
appears across the motor which thus rotates. 

The card sensor photodetector signals are amplified by 2-transistor 
circuits and fed to {\bf DI(3)}\ldots{\bf DI(6)}. These transistors are cut 
off by {\bf SenseEn} when the motor is not running. 2 of the sensor 
outputs are diode-ANDed to give the {\bf RdEn} signal which enables the 
read amplifiers. 

Bit 4 of the I/O register is latched in U8a, again by {\bf CROut}. The 
output of this flip-flop, {\bf WrD}, disables the write drivers when it 
is set. It appears to be set throughout read operations but cleared 
during write operations.

The 4 write circuits are essentially the same, so only track A will be 
described. Bit 0 of the I/O register is copied into U8b, which drives the 
inverter U7c. When U8b is set, the output of U7c is low, saturating the 
transistor and making the voltage on its collector close to +12V. The 
coupling diode is reverse-biased, so no current flows in the head 
winding. When U8b is set, the transistor is cut off, and a current flows 
through the head from the =12V supply rail via the coupling diode and 
2.7k resistor. U9e clamps the head drive signal to ground, preventing 
writing during read operations. 

There is one difference for the `S' clock write channel. The output 
flip-flop, U5b, is loaded by {\bf CRSOut} rather than {\bf CROut}. This 
makes it easier to delay the clock pulse with respect to the data pulses.

The 4 read amplifiers are, again, identical. The signal from the head is 
amplified by an operational amplifier such as U4, and fed to a 
discrete-transistor amplifier and schmitt trigger circuit. The latter is 
enabled by {\bf RdEn} from the card sensor circuitry when there is a card 
in the reader track.

The output of the clock channel is fed to a 2-transistor circuit which 
produces a positive-going pulse on {\bf CRRdClk} for a magnetic 
transition of either polarity on the card. This signal loads the outputs 
of the 3 data channels, suitably buffered, into the read flip-flops such 
as U10b. These can be read into the processor I/O register via the 
associated open-collector inverters, such as U9c. When there is no card 
in the reader, {\bf RdEn} being deasserted asserts {\bf ClrRd}, forcing 
all the read flip-flops to be set and thus the outputs of the inverters 
to be in the high-impedance state. Thus other devices can drive the i/O 
register inputs. 

{\bf CRRdClk/} is fed to the {\bf I/O Interface} PCB where it sets the 
SR flip-flop U4c, U4d. This causes the first gate of U9 to assert {\bf 
I/O flag} when a card reader I/O instruction is executed. This is used to 
indicate the presence of new data in the read flip-flops. This flip-flop 
is cleared by U2d when {\bf I/OStb} is asserted at the end of an I/O 
instruction with bit 9 set (this is detected by U2a on the {\bf Clock} 
PCB along with {\bf Q(1)} being set, that is select code 2.

\section{Cassette drive}
The digital cassette drive fitted to the HP9830 uses digital-grade tape 
in cassettes similar to audio Compact Cassette. Unlike normal audio 
cassette recorders, though, the tape is transported simply by turning 
the spools, there is no capstan and pinch roller. Although this means the 
tape does not travel at constant speed, the encoding system used on the 
HP9830 in not sensitive to this.

The entire width of the tape is used at once, the cassettes are not 
turned over like audio cassettes. Two tracks are recorded on the tape. A 
pulse on one track indicates a logic 0 bit. A pulse on the other track 
indicates a logic 1 bit. And a pulse on the 2 tracks simultaneously is 
used as a start-of-byte marker. This is known as `Bit-Mark-Sequence' or 
`BMS' in some documentation

An optical EOT sensor detects the clear leader tape in the cassette. It 
consists of a small filament lamp and light-dependent resistor (LDR) 
mounted so that light from the bulb is reflected off the cassette shell 
and onto the LDR when the clear leader (rather than opaque tape) passes 
in front of the sensor assembly.

\subsection{Motor control}
The tape drive is fitted with a pair of permanent-magnet DEC motors, one 
for each tape spool. The motors are mounted on a metal beam, pivoted at 
the mid-point. This beam is rocked by a pair of solenoids, and this 
engages the motor spindle with a rubber-tyred wheel attached to each 
tape spindle.

The {\bf Motor Control} PCB selects a particular motor and its associated
solenoid to control the tape direction and regulates the speed of that
motor. The direction control system takes in 2 signals from the {\bf Tape
Controller} PCB. {\bf MotorOn/} goes low to start tape motion, causing the
output of U4c to go high, enabling U4b and U4d. The {\bf Dir} direction
control signal, inverted by U4a thus causes the output of one of those
gates to go low., turning on the associated PNP transistor. This drives a
pair of NPN transistors, one of which energises the solenoid, the other
grounds the negative side of the selected motor. 

The motor speed controller senses the current through the selected motor 
by measuring the voltage drop across a 10$\Omega$ resistor in series with 
it (this is the resistor connected between TP2 and TP3 on the {\bf Motor 
Control}) PCB. This voltage is amplified by U1 and compared with a 
reference level by U2. The output of U2 controls the motor pass 
transistor, Q9 on the {\bf PSU} PCB (it is located there simply because 
it needs to be fitted on a heatsink), thus controlling the motor current 
and therefore the motor speed.

The {\bf Speed} input from the {\bf Tape Controller} PCB is applied to 
U3a, the output of which varies the reference voltage level to U2. When 
{\bf Speed} is low. the reference voltage is increased, so the motor 
turns faster.

The output of the LDR in the optical EOT sensor is converted to a digital
signal by U1 on the {\bf Tape Drive Connector} PCB acting as a comparator.
When the tape leader is detected, {\bf EOT} goes low, causing the output
of U1a on the {\bf Tape Interface} PCB to go high. If the motor is
running, monostable U6 is triggered, and when this times out, U5b is set
(since the output of U4b must be 1 when {\bf MotorOn/} is low). This
asserts {\bf SpeedClamp} via U4c. 

When {\bf EOT} goes high again (tape, rather than leader in front of the
sensor), U5b is directly cleared, deasserting {\bf SpeedClamp}. U5b is also
set when there is no tape in the drive ({\bf CassSw} is low) or during
power-on initialisation ({\bf ClrMark}, from U17f on the {\bf Tape
Controller} PCB is low). 

Back on the {\bf Motor Control} PCB, {\bf SpeedClamp} causes U3b to 
clamp the motor speed control line to the voltage of its associated zener 
diode. This prevents the motor running too fast and causing damage when 
the tape stalls.

\subsection{Low level read/write system}
This section translates between the conventional clock and data signals and 
the BMS format described earlier. It also interface to the tape head itself.

For a write operation, the output of U5b on the {\bf Tape Controller} 
PCB goes high, asserting {\bf Write}. On the {\bf Read/Write} PCB, U4c 
ANDs this with the output of the write-protect switch ({\bf WpSw/}), 
preventing writing on protected cassettes. {\bf WrEn} enables the write 
encoder circuit.

During writing, if {\bf WrData} is high when {\bf WrClk} goes high, the 
output of U8b goes low, and forces {\bf WA} high via U7a. Similarly, if 
{\bf WrData} is low (making the output of U6a high) when {\bf WrClk} 
goes high, the output of U8c goes low and that of U7b, {\bf WB} goes 
high. Finally, when {\bf WrMark} is asserted, the output of U8a goes low, 
asserting both {\bf WA} and {\bf WB}. In this way the incoming data is 
converted to the BMS format. 

The head drivers, located on the {\bf Tape Head} PCB are identical in 
operation, so only the `A' track will be described. {\bf WA} is inverted 
by U1 and thus the outputs of U1b and U1c are in antiphase. This provides 
the signal to the head winding. The power to U1 is controlled by a 
transistor on the {\bf Read/Write} PCB which is turned on via U6e 
during writing, there is no write current in the head at other times.

The 2 read amplifiers are identical, so as before I will only describe 
the `A' channel. The output from the head winding is amplified by U2a on 
the {\bf Tape Head} PCB and fed, as an analogue signal ({\bf RA}) to the 
comparator U1b on the {\bf Read/Write} PCB. The threshold of this 
comparator is determined by its current state via the 2 transistor 
circuit connected to its output, thus providing hysteresis and also by 
the state of the {\bf Speed} signal via U6f, U4d and the associated 
transistors. When the tape is running fast for searching, the comparator 
threshold is increased, improving the noise immunity. The output of U1b 
is fed to U4a, which is enabled during reading by U6e. The {\bf TTLRA} 
and {\bf TTLRB} signals at the outputs of U4a and U4b are logic signals 
that indicate when pulses have occurred on the tape tracks.

When there is a pulse on both tracks at the same time, the output of U7c 
goes low, clearing U3a. This asserts {\bf RdMark}.

When a pulse occurs on track `A' and no mark has been detected, 
U7d clears U5b, thus making {\bf RdData} high. When a pulse occurs on 
track `B' or a mark has been detected, U5c sets U5b, making {\bf RdData} 
high.

A pulse on either (or both) tracks makes the output of U5a pulse low. 
This triggers the monostable U2. During reading, when no mark has been 
detected, the output of U5d is high, and thus the output of U6b low. When 
U2 is triggered, therefor, its Q/ goes low causing {\bf RdClk} to pulse 
low via U5b and U6c.

Thus the BMS data on the tape is separated into clock, data and mark 
signals.

\subsection{Tape control}
The {\bf CO(n)} peripheral select lines are decoded on th {\bf Tape 
Interface} PCB, and when select code $1010_2$ is detected, the output of 
U13a goes high. If {\bf CEO} is also high, U11c asserts {\bf StatEn} 
enabling the gates in U7, which pass various status signals to the {\bf 
SI(n)} inputs to the I/O register. If {\bf CEO} is low, {\bf TapeSel} is 
asserted by U11b, and, this, after being buffered by U11a, enables the 
data output gates in U8 and U9 so the tape data can be read into the I/O 
register (the source of this data will be explained shortly). 

On the {\bf Tape Controller} PCB, {\bf TapeSel} triggers monostable U10. 
U10 enables decoder U8, which decodes {\bf SO(0)}\ldots{\bf SO(2)} and
asserts {\bf RunCmd/} for any of the 4 read commands or the write command.
This latches the {\bf SO(n)} lines in the command latch U1. The 2 
least-significant bits of U1are fed to the {\bf Motor Control} PCB via U6a 
and U6b, to control the tape speed and direction.

{\bf RunCmd} also sets the run flip-flop U4b, which asserts {\bf MotorOn} 
via U6c, starting the tape motion. The run flip-flop is cleared at the 
end of the tape ({\bf SpeedClamp} goes high, thus clocking a 0 into U4b 
via U16a and U17e), or when {\bf Stop} is asserted by U12c. This occurs 
at power-on (from U17f), when a stop command is given to the interface 
({\bf StopCmd/} is set low by U8), or when there is no tape in the drive.

Manual rewinding is controlled by U4a. This is set by the `Rewind' key on 
the keyboard, and its output causes the output of U5c to go high if 
there is no tape operation in progress. This forces all 3 motor control 
signals low, causing the tape to rewind at high speed. U4a is cleared 
either when a tape command is started ({\bf RunCmd} clocks a 0 into U4a), 
or when the tape ends or when one of the `stop' conditions mentioned 
earlier occurs.

\subsection{Tape data register}
Data is stored on the tape in 9-bit characters, each character is 
preceded by a mark. Of the 9 bits, 8 of them are transfered to or from 
the least significant byte of the processor I/O register. The centre bit 
is, however, loaded from bit 3 of the command latch U1 on the {\bf Tape 
Controller} PCB and indicates the file marker character. The centre bit 
of the nine is used for this since it is in the same position relative to 
the marks no matter which way the tape is being read, enabling file 
markers to be found during both forward and reverse scans of the tape.

The data register consists of the D-type flip-flop U20b and the two 4-bit 
registers U19 and U18, cascaded in the usual manner. U15a and U15b 
provide a parallel load facility for the most significant bit. 

The timing of the data transfer is controlled by the 10-state counter U3. 
U7c asserts {\bf WrMarkEn/} when this counter gets to its final state of  
$1001_2$. Data bits are transfered in the 9 states when {\bf WrMarkEn/} is 
not asserted. 

Although these 2 sections are common to both reading and writing data, it 
is simpler to consider their operation and that of the associated control 
in these 2 cases separately

\subsubsection{Tape writing}
When the tape system is selected by the CPU during a write command, {\bf 
LdSR} is asserted by U5a, thus transferring data from the processor I/O 
register to the tape data register.

Since {\bf write} is asserted by U5b during write commands, the write 
clock oscillator U2 and U9 is enabled, The reset-to-9 input of U3 is 
enabled (and the reset-to-0 disabled via U17d) so when the write 
operation is started, U11b is set by the rising edge of {\bf write}, 
forcing U3 to state $1001_2$ and asserting {\bf WrMarkEn/}. This enables 
U13b via U14f, casing the first {\bf RawWrClk} pulse to assert {\bf 
WrMark} and thus write a mark on the tape. {\bf WrMark} also clears U11b 
via U14d, thus enabling the counter U3 to count. 

While {\bf WrMarkEn/} is not asserted, U7d is enabled, and the shift
register is clocked by the write clock oscillator. U7d also provides the
{\bf WrClk} signal to the data encoder described above. The data input to
the encoder is connected to the least significant output bit of the tape
data register, Thus the 9 bits in the shift register are transfered to 
the tame, then {\bf WrMarkEn/} is asserted to write the marker for the 
start of the next 9 bit word, and the sequence repeats. 

\subsubsection{Tape reading}
When the tape is read, the write clock oscillator is disabled since {\bf 
Write} is low. The output of U7d is forced high, and thus U7b passes the 
read clock signal, {\bf RdClk} from the data decoder to the shift 
register. When a data bit is detected on the tape, it is shifted into the 
data register, The bit counter U3 is also clocked by {\bf RdClk}, and is 
set to 0 when U20a is set by a mark being read from the tape. {\bf 
WrMarkEn} is asserted by U7c when 9 bits have been read from the tape.

The parallel outputs of the data register are transfered to the processor 
I/O register via the data output gates in U8 and U9 on the {\bf Tape 
Interface} PCB, enabled by U11a

\subsection{Tape flag and interrupt}
The tape flag signal is produced by U12b on the {\bf Tape Controller} 
PCB. When the tape system is writing the output of U6d is forced low, 
forcing the output of U12a high. Therefore the flag signal is controlled 
by U15c. Its output goes low, causing a flag, when {\bf WrMark} is 
asserted, indicating that a new word should be loaded into the shift 
register. U11a is set at the start of a write operation, inhibiting the 
flag signal for the mark that is then generated.

During reading, U15c's output is always high. The flag is generated by
U12a, normally when 9 bits have been read from the tape, since U7a's
output is forced high by the {\bf Bit4} output of the command latch being
low. However, by setting this bit, the tape flag will only be asserted
when {\bf Bit4Out/} from the data registers is asserted after 9 bits have
been read, that is when a file marker has been detected. As mentioned
above, this is independent of the direction of tape movement. 

The tape flag signal sets U5a on the {\bf Tape Interface} PCB, thus 
asserting {\bf BusI/ORd/}. This causes the output of U7c on the {\bf I/O 
interface} PCB to go high, triggering the monostable U8 and copying the 
data from the tape data register into the I/O register. U8 also sets the 
flip-flop U13a, asserting the processor I/O flag via the second gate in 
U9. 

During a scan for file markers (that is, {\bf Bit4} is high and therefore 
so is  {\bf BuffBit4}), the tape system can interrupt the processor. When 
the tape system is not selected by the processor and {\bf BuffBit4} 
is high, the reset input of U14a is deasserted. This flip-flop is 
therefore set by a rising edge at the output of U2c,which can occur in 3 
ways : if the tape runs to the clear leader, and thus {\bf BuffSC} is 
asserted causing the output of U1c to go low; if the cassette is 
removed, causing the output of U1b to go low; or if the output of U2b 
goes low, which occurs when the file marker character is found. The last 
occurs when bits 2\ldots 5 of the tape data register are all set and a 
tape flag occurs, but since {\bf Bit4} must be high to enable the 
interrupt system in the first place, the centre bit ({\bf Bit4Out/} of 
the shift register must also be asserted to enable {\bf TapeFlag/} as 
described above. 

Interrupts other than the file marker being found cause the output of U3a 
to go low, setting U5a and causing {\bf BusI/ORd/} to be asserted, which 
has the effects described earlier.

When the interrupt occurs and U14a is set, {\bf KeyDn} is asserted via 
U3c, interrupting the processor. U3b pulls {\bf SI(1)} low, thus enabling 
the processor to determine the source of the interrupt.

The output of U14a, {\bf StopTape/} causes the output of U12c on the {\bf 
Tape Controller} PCB to go low, thus clearing the run flip-flop U4b and 
stopping the tape.

\subsection{Beeper}
The HP9830 incorporates a fixed-frequency, fixed-duration beeper which is 
described here simply because it is located on the {\bf Tape Interface} PCB.

The otherwise-redundant {\bf CROut} signal (used for card reader output 
in the HP9810 and HP9820 and described in that section) triggers the 
monostable U12 when a beep is required. This enables U15c, passing the 
output of the oscillator U15a, U15b to the loudspeaker driver transistor 
via U15d. Thus the speaker is driven. The positive side of the speaker is 
connected to the output of an emitter follower, the base of which is 
connected to a 22$\mu$F capacitor. When U12 is not triggered this capacitor 
is charged via the diode and 470$\Omega$ resistor. When U12 is triggered 
and the beep is produced, this capacitor discharges via the 3.9k$\Omega$ 
resistor thus gradually reducing the voltage applied to the loudspeaker 
and giving a decaying amplitude envelope.

