APPENDIX B F\RTECKNING \VER ALLM[N TEKNISKINFORMATION .bl _____________________________________________________ REFERENSER .bl __________ P[RM B 01: .bl _________ Data flow supercomputers. Recursive machines and computering technology Data driven system for high speed parallel computering. MAUD:a dynamic single-assignment system A data flow multiprocessor. Principal components of a data flow computer. Small firm has big ideas for multiple microprocessors. Predicting thermal characteristics of ventilated electronic enclose. Applaying the hamming code to microprocessor-based system. Choose cabels with care to optimize system design. Singel error correction code miximizes memory system efficiency. Board applies codes to small-computer memory. RAM-based multiplexer systems can save big chunks of hardware. Multiport register file stremlines signal processing. Shared memory system. Asynchronous dual-port RAM simplifies multiprocessor systems. Functionally parallel architecture for array processors. Vi {r |verhopade av best{llningar (FEM-firma) Microprogrammable chips blend top performance with 32-bit structures. Bipolar arithmetic chip speeds 68000's mat throughtput. Arbiters, priority acess conflicts and "glitch" problem. Packing a signal processor onto a singel digital board. Dual-port RAM hikes throughput in input/output controler board. !! Innovative Architectual and software techniques result in low cost high performance array processor. Avancerad bildbehandling skiljer agnarna fr}n vetet. N{stan-superdator kostar bara en tiodel. Superdator marknaden m}ngdubblas p} 10 }r: Computer Sweden 850125 Handling real-time images comes naturally to systolic array chip. Associative memory calls on the talents of systolic array chip. Systolic array chip matches the pace of high-speed processing Carring out division by addition reducees hardware complexity: Computer Design june 1975 Radix conversion: Donald E. Knut Managing the flow of data is easy with programmable multipexer: Electronics/May 11, 1978 Bipolar arithmetic chip speeds 68000's math throuhput: Personal-computer engineering add-ons and add-ins. IBM n{r en hel indistri. Industriell Datateknik 1984:4 R{knar som f}. Industriell Datateknik 1984:6/7 !! P[RM B02: .bl ________ Giants in small packages: IEEE Spectrum feb 1982 Architectual and software issues in the design and application of peripheral array processors: IEEE sep 1981. Precompilation of fortran programs to faciliate array processing. Array Processors: A selected Bibliography A proposed standard for binary floating-point arithmetic Analysis of proposal for the floating-point standard Applications of the proposed IEE 754 standards for floating- point arithmetic Underflow and the denormalized numbers Programmable array processors crunch numbers effortlessly Arithmetric chips assume greater importance as uC users demand faster response C-MOS cip set stremlines floating-point processing Hardware multiplication techniques for microprocessors systems An introduction to vector processing LSI hardware implements signal processing algorithms Comparison of selected array processor architectures Array processors provides high throughput rates Intelegent memory holds the key to a limitless array of computers Multiplier-accumulator derives high performance from 1-um CMOS Dense static RAM speeds data access in memory-intesive systems Floting-point array processors evolve into tailorable systems CMOS signal processors push to highest througput of all A statistical study of the aqccuary of floating point number system On the precision attaniable with various floating-Point number system Roundings in floating-point arithmetic !! P[RM B03: .bl ________ Matrix computations on an associtiv processor. A content addressable distributed logic memory with applications to information retrieavel. Supercomputer arichitecture. Associativ and parallel processors. Vector extensions to LRLTAN. Associtve processors architecture- a survey. Solving some mathematical problems by associtve processing. TSE computers (optisk dator). Some computer organizations and their effectivness. Design motivations for multiple processor microcomputer systems. Interconection system approches for minimizing data transmission problems. Arithmetic processor chips enhance microprocessor system performans. Making minframe mathematics. Reducing system interconnection with multivaule logic. Hardware multiplication techniques for microprocessor systems. Dedicated multiplier ICs speed-up processing in fast computer systems. Medium-speed multipliers trim cost shrink bandwith in speech transmission. Multiplier/divider hardware design accelerates microprocessor throughput. Multiprocessor memory organization and memory interference. Multiprocessor interconnection. Analys of multiple-microprocessor system architectures. The three-dimensional computer: a multiplan array processor. Interprocess communication for multi-microcomputer systems. Parallel processors architectures- part: General purpose systems. Multi-microprocessors: An overview and working example. Predicting queue performance on a programmable handheld calculator. !! P[RM B04: .bl ________ Digital group selectors Synchronization N-channel asynchronous arbiter resolves resours allocation conflicts. System capabilities get a boost from a high-powered dedicated slave. Packing a signal processor onto a single digital board. Dual-port RAM hikes throughput in input/output controler board. Micro-control for parallel asynchronous computers Time-shared memory-processor interface. A large scale, homogeneous, fully didtributed parallel machine. A multiple instruction stream processor. Process coordination in multimicroprocessor systems. SPDM- a subprocessor with dynamic microprogramming. A structured multimicroprocessor system with deadlock free operation schema. Implement digital filters efficiently with a specally cofigurated computer. Hexadecimal signatures identify troubelspots in microprocessor systems. A computer capable of exchanging processors for time. A new hierachical array processor system. Beskrivning av minnessystem 128x44. Boost bit-slice microsequencer speed: Choose from eight different circuits. Signal analysers (HP). Computer interconnection structures: Taxonomy, characteristics, and examples. Motorol's advanced computer system on silicon. Microprogram med hj{lp av PAL. An implementation guide to a proposed standard for floating-point arithmetic. !! P[RM B05: .bl ________ Digital filter design. Reducing roundoff noise in digital filters. First single-chip digital output correlator compares data at a 20-MHz rate. Interconnection network for SIMD machines. Multiprocessor organization- a survey. A multiprocessor approach to numerical analysis: An application to gaming problems. An approach to modular multicomputer systems. A hierarchically structured mult-microprocessor system. User-oriented turning in a microprogrammable computer. Poly processors system PPS-1. Parallel processing with the perfect shuffle. A shuffle-exchange network with simplified control. Developments and directions in computer architecture. Asynchronous control arrays. Macro E-nets for representation of paralell systems. Develop a multiple-instruction-stream single-chip processor. The possible impact of software trends on microcomputer architecture. Superpower computers. Integrated arithmectic processing unit enhances processor execution times. Numerical interpolation for microprocessor-based systems. Multiplying with a microcomputer. Tough mathematical tasks are child's play for number crunchers. Approach to unified bus architecture sidsteps inherent drawbacks. SMS 101- A structred multiprocessor system with deadlockfree operation scheme. !! Multi-microprocessors: An overview and working example. VLSI computering: A tough nut to crack. Computer processes multiple instruction sets, multiple data streams. Speech recognition by computer. GOP: Image processing 100 000 times faster. GOP: En skr{ddarsydd bildgehandlingsdator. GOP: A fast and flexible processor for image analysis. Image processing by computer. Associative processors: A panacea or a specific? Floating point adder VLSI projected for 1981. Unit multiplies two 64-bit numbers in 284 nanoseconds. Applications of vector processing. !! P[RM B06: .bl ________ Memory structure speeds generation of pseudonoise sequences. A free-text retrieval system using hash codes. Hash index helps manage large virtual memory. Extendible hashing- a fast access method for dynamic files. Generation and uses of pseudo random binary sequences. Random number generation and monte carlo methods. A simple method for determination of feedback shift register connections for delayed maximal-length sequences. Crossscorrelation properties of pseudorandom and related sequences. Pseudo-random number generator based on binary and quinary maximal- length sequences. Computer methods for sampling from the exponential and normal distributions. Computional complexity of probalistic turning machines. Fast probalistic algorithms for verification of polynomal identites. Probalistic algorithms. Word problems requring exponential time. Determining the equivalence of algebraic expressions by hash coding. Universal classes of hash functions Performing of a parallel hash hardware with key delition. Parallel hashing algorithms. Hashing functions. Partial-match retrieval via the method of superimposed codes. VEGAS- An adaptive multi-dimensional integration program. Monte carlo simulations of lattrice gage theories. Monte Carlo calculation as an aid in teaching solid-state diffusion. A retrospective and prospective survey of the Monte Carlo method. Monte Carlo theory and practice. !! P[RM B07: .bl ________ Computer queueing analysis on a handheld calculator. Queuering models of computer systems. Approximate solution of queueing models. Measuring and calculation queue length distributions. An introduction to data compression. Information preserving codes compress binary pictorial data. Huffman coding. Data compaction in computer systems. Example of data encoding. Singel 12-bit multiplier allows 32-bit floating point arithmetic. Speech processing system described at ICASSP 80. New direction in computer system architecture. Datafl|de spolar bort von Neumans dator Use PLD's to shrink complex, discrete loic designs State-machine approach speeds logic design Algorithm speeds nonrestoring division in uprogrammed systems Interface arrangement suits digital processor to multiprocessing Scientific computer simulates VLSI circuits in record time Memory-management.chip schemes respond to super-uC requirements Use SCSI devices for multiprocessor, smart-I/O systems Low cost, dual-port RAM design delivers high performance Simple logarithms speed uP math operations